(1) Field of the Invention
The present invention relates to an adjacent code system and more particularly to a system in which the output signal of a binary counter appears at the output of a decoder that has a selected line for each state of the binary counter. As part of the operation of the system the output signal of the binary counter is converted to an adjacent code. An adjacent code can be defined as any code that produces only one bit change for each successive state change in a counting sequence. The conversion to an adjacent code takes place in the present invention to enable the output signal of the binary counter to be presented without "glitches" at the output of the decoder. The term "glitches" will be explained later.
(2) Description of the Prior Art
Digital counters are widely used in present-day circuit applications for a variety of functions. For example, they are frequently used for scanning keyboards and switch matrices. They are used to scan output displays, such as the well-known seven-segment LED displays. They are also used for timing, for instance, in real time clocks and as baud rate generators in serial communications. Many other such applications also exist.
There are many codes that can be used to represent the states of a digital counter. In the case of standard binary systems, each state is assigned a unique string of binary digits, called bits. Each bit is either a logic "0" or a logic "1." One of the most common codes used is the "binary" code in which each number in a set of integers from "0" to "2.sup.n -1" is expressed as a weighted sum of "n" bits and each bit is weighted according to its position in the string. The bit that is located at the farthest position to the right is called the least significant bit and has a weight of 2.sup.0. The next bit to the left has a weight of 2.sup.1. The weight increases by a factor of two with each successive bit. The bit that is farthest to the left is the most significant bit and has a weight of 2.sup.n-1.
A binary counter normally sequences through these binary codes in the ascending order of their equivalent numbers. Some binary counters operate in descending order. While the binary code can be efficiently implemented in counters, this approach has the disadvantage of producing glitches when the output of such a counter is decoded.
Decoding is the process of identifying which state a counter is in, i.e., its present value. This process often means the assigning of one output line of the decoder to each state of the counter. The condition of this output line signifies whether or not the counter is in the state assigned to that line. There are many ways to do this. Some counters are self-decoding; in that case, each output line of the counter corresponds to a different state. Other counters require additional combinations of logic to decode their states. For counters requiring decoding, the use of only combinational logic for decoding may result in decoding glitches.
The errors called "glitches" consist of unwanted, narrow pulses that appear in the output of a logic gate. They occur when two or more inputs to a gate are intended to change simultaneously, but fail to do so. The gate output may change once when the first input changes and again when subsequent inputs change. For instance, when going from one to two in binary, the change is from 01 to 10. If on a counter the second bit changes prior to the first bit, the output goes from 01 to 00 to 10. If the first bit changes prior to the second bit the output goes from 01 to 11 to 10. The intermediate states formed at the output of a logic gate are undesirable narrow pulses called glitches. In this way, multiple output changes can take place when either none or one is desired. One way of avoiding such glitches in the decoding of counting systems is to use "adjacent" codes. As mentioned previously, an adjacent code has the property of requiring only one bit change for each successive state in a counting sequence. This property is significant, because it prevents glitches when the decoding of states takes place. This is because multiple input changes to the decoding gates cannot occur for any state change. Unfortunately, a binary code is not "adjacent" and decoding by using combinational logic will generally produce glitches.
This problem can be avoided by using sequential logic. One way is to decode the binary counter one state early for each state with combinational logic. This decoded state can then be latched simultaneously with the changing state of the counter. This is done by using a counter clock to serve also as the latching clock. The counter clock in such a case must have a frequency that is twice that of the "least significant" bit of the binary counter. In this way, the glitches output from the decoder are hidden by the latch without adding clocking delays to the decoder. The disadvantage of this solution is that a counter clock is required to latch the decoder outputs.